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A Review of Structural Testing Methods for ASIC based AI Accelerators


Umair Saeed, Irfan Ali Tunio, Majid Hussain, Fayaz Ahmed Memon, Ayaz Ahmed Hoshu, and Ghulam Hussain


Vol. 23  No. 1  pp. 103-111


Implementing conventional DFT solution for arrays of DNN accelerators having large number of processing elements (PEs), without considering architectural characteristics of PEs may incur overwhelming test overheads. Recent DFT based techniques have utilized the homogeneity and dataflow of arrays at PE-level and Core-level for obtaining reduction in; test pattern volume, test time, test power and ATPG runtime. This paper reviews these contemporary test solutions for ASIC based DNN accelerators. Mainly, the proposed test architectures, pattern application method with their objectives are reviewed. It is observed that exploitation of architectural characteristic such as homogeneity and dataflow of PEs/ arrays results in reduced test overheads.


Accelerator, Artificial Intelligence, Design-for-Testability, DNN, testing.