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Title

Design of High Throughput and Low Latency Double Precision Floating Point Arithmetic Unit for Space Signal Applications

Author

Ponduri Sivaprasad, Dr.V.Anandi, Dr.Satyanaryana Murthy

Citation

Vol. 22  No. 9  pp. 808-815

Abstract

For space signal processing systems, reliability, accuracy, and performance are major concerns for the detection of accurate phase estimation, for and most of the functionality of the system, the data is acquiring high speed and supervising continuously for validation of correct data. For more accuracy, fixed points arithmetic operations have got lot of data losses and single-precision floating point operations also has data losses. All existing double-precision floating point arithmetic operations utilizes dual rail coding to perform complete detections and also required the circuit to receive acknowledge on completion execution and it leads to worst-case delay irrespective of the actual completion time. With help of modified double precision floating point operations, we can obtain more reliability by using memory based synchronization architecture and high accurate phase detection. In space applications, milli degree estimation is major challenge and plays important role, in order to estimation milli degree, the Double Precision Floating Point (DPFP) based arithmetic operations are designed using Verilog hardware description language and synthesized with help of Xilinx Design Suite 14.7 ISE software tool and finally implemented on Virtex-5 FPGA development board. All arithmetic operations use ternary logic at lower level module design to optimize area and latency. The proposed architecture of double precision floating point arithmetic operations is good enough in terms of power optimization, high speed, optimal delays, hardware utilizations (Slices and LUT’s) and smaller-sized edge device. The synthesized results show that proposed DPFP based ALU design for estimation of milli-degree reduces the overall latency to 23%, throughput is improved by 13% and power consumption is reducing to 31% as compared to existing works.

Keywords

Floating point based ALU, Ternary logic, Signal processing, milli-degree estimation, FPGA.

URL

http://paper.ijcsns.org/07_book/202209/202209105.pdf