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High Throughput Multiplier Architecture for Elliptic Cryptographic Applications


Gutti Naga Swetha and Dr. Anuradha M.Sandi


Vol. 22  No. 9  pp. 414-426


Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex ? 5 and Xilinx Virtex-7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2^163 ), GF(2^233 ) and GF(2^283 ). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex ? 5 and by 25.13% and 47.75% for Xilinx Virtex ? 7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex-5 and Virtex-7 over GF(2^233 ) and GF(2^283 )are also very satisfactory.


ECC, HTCC, Point Multiplication, FPGA